1. Field of the Invention
The present invention relates to a data control apparatus connected to a central processing unit that processes data and to a main storage unit that stores therein the data, to control output of the data, and a data control method and a data control program.
2. Description of the Related Art
Conventionally, when certain data is output to a cache memory of a central processing unit (CPU) in a computer system, because the system has data to be immediately output after the CPU accepts a data output request and also has data to be output after the CPU queries an output destination and obtains permission, it is necessary to prepare data queues (storage units) that temporarily store therein these data respectively (for example, Japanese Patent Application Laid-Open No. H08-063954).
Specific explanation is made with reference to FIG. 11. A computer system shown in FIG. 11 includes a CPU 110 and a CPU 111, a data control apparatus 120 and a data control apparatus 121, and a main storage unit 130 and a main storage unit 131. These are formed into clusters, respectively, and thus data transfer between the clusters is performed by using the data control apparatus 120 or the data control apparatus 121. Besides, the data control apparatus 120 is formed of a plurality of data queues (MIQ 120a, MSQ 120b, MOQ 120c, and MBQ 120d) that temporarily stores therein data, and of a selector 120e that performs arbitration of data output from the MOQ 120c or the MSQ 120b to the main storage. Similarly to the data control apparatus 120, the data control apparatus 121 is also formed of MIQ 121a, MSQ 121b, MOQ 121c, MBQ 121d, and a selector 121e. 
When the CPU 110 or the CPU 111 outputs data in a cache memory of its own to any other device, to keep sequence of the data, the data queue (e.g., MIQ 120a) needs to output data for the same destination to the output destination in the order in which the data is output from the CPU, and thus the data queue controls received data using FIFO (First In First Out).
Based on the configuration, when the data in the cache memory of the CPU 110 is output to the CPU 111, the CPU 111 already establishes an acceptable state of the data because the request is sent from the CPU 111, and therefore, the CPU 110 immediately outputs the data to the data queue.
Specifically, when the data in the cache memory of the CPU 110 is output to the CPU 111, the CPU 110 outputs the requested data to the MBQ 120d of the data control apparatus 120. The MBQ 120d that receives the data checks that a communication channel is unoccupied, and then outputs the data to the CPU 111 which is the output destination.
Meanwhile, when the data in the cache memory of the CPU 110 is output to the main storage unit 131, the CPU 110 outputs the data to the data queue. However, the data queue that receives the data cannot determine whether the output destination is in the acceptable state, and thus the data queue that receives the data makes a query whether the main storage unit 131 as the output destination is in the acceptable state, and outputs the received and stored data after permission is granted.
Specifically, when the data in the cache memory of the CPU 110 is output to the main storage unit 131, the CPU 110 outputs the data to the MOQ 120c of the data control apparatus 120. The MOQ 120c queries the MSQ 121b of the data control apparatus 121 about whether the main storage unit 131 is in the acceptable state, and outputs the received data to the MSQ 121b after permission is obtained. Thereafter, the MSQ 121b outputs the received and stored data to the selector 121e of the data control apparatus 121, and the selector 121e arbitrates the received data and outputs the data to the main storage unit 131.
The conventional technology, however, requires a plurality of memories (MOQ or MBQ) with a processing speed equal to that of the CPU to improve system performance, and thus there is a problem that cost for construction of the system increases. Specifically, the memory (MOQ) for data output from the CPU to the main storage unit and the memory (MBQ) for data output to another CPU are required, and preparation of the both memories with the processing speed equal to that of the CPU causes an increase in cost.